When transmitting digital data at a very high bit rate, the signal needs to be regenerated periodically, both in amplitude and in phase. To do this, it is necessary to have a clock which has been extracted from the transmitted data, and this gives rise to a difficult filtering problem when the codes used are of the NRZ or of the RZ type since there are few transitions. Apart from passive filter devices such as surface wave filters, for example, phase lock loops are used. In this application which consists in isolating a particular frequency component from a spectrum, the loops are known as "narrow" loops (having a natural angular frequency which is small compared with the central angular frequency), thereby giving rise to a narrow acquisition band and to long acquisition time.
Several circuits are known for mitigating these drawbacks:
A voltage controlled crystal oscillator may be used which makes it possible to have a central frequency of sufficiently high accuracy to be within the acquisition band under all circumstances. Acquisition time is then short since the initial frequency difference is small. However, using a crystal at high bit rates (greater than 34 Mbit/s) gives rise to high costs and in addition does not avoid the need for any adjustment.
A frequency lock loop may be added to the initial phase lock loop. One such system is described in U.S. Pat. No. 4,015,083 relating to a circuit for correcting synchronization errors. This circuit generates an error voltage proportional to the frequency difference between its input and its output, and the error voltage is used to provide frequency locking. This apparatus gives rise to a complex circuit requiring difficult phase adjustments.
Another method consists in using an external sawtooth generator whose output is added to the control voltage of the voltage controlled oscillator. This causes the oscillator to sweep through frequencies. Its passage through the locked condition is detected by using a second phase comparator operating in quadrature with the first, together with a lowpass filter and a level comparator. Locking causes a DC component to appear at the output from the second phase comparator and this is detected by the lowpass filter and the level comparator, at which point the sawtooth sweeping signal is switched off. This apparatus requires a large number of external components and, in addition, suffers from low immunity to jitter in the input signal.
The aim of the invention is to mitigate the drawbacks of known solutions, and to obtain apparatus which is simple to make and easy to implement.